This invention relates to power MOSFET devices and more specifically relates to a novel low voltage power MOSFET with a minimized figure of merit for use in very low voltage applications with maximum efficiency.
Power MOSFETs are well known and a typical device and a process for its manufacture is described in U.S. Pat. No. 5,795,793 entitled PROCESS FOR MANUFACTURE OF MOS GATED DEVICE WITH REDUCED MASK COUNT issued to Daniel M. Kinzer. The device of that patent has a planar type geometry in that the invertible channels under the gate electrode are in a common plane with the surface of the silicon die containing the channel regions.
Another well known type of geometry used for power MOSFETs is the trench geometry in which the invertible channels are formed along the vertical walls of trenches etched into the silicon surface.
It was generally believed that the trench geometry is preferable to planar geometry for very low voltage MOSFET devices, for example, these having a reverse breakdown voltage of 30 volts or less. These very low voltage devices, which are commonly used in switch mode converters for providing a regulated d-c voltage from a battery for portable electronic devices such as lap top computers, should be as efficient as possible to permit maximum battery life. Thus, devices having the smallest possible figure of merit, which is the product of drain to gate charge Q.sub.GD and on-resistance R.sub.DSON, are most desirable in these applications. The conventional wisdom of the art was that the trench geometry has an inherently smaller Q.sub.GD than a planar device; and that similarly reducing the Q.sub.GD of a planar geometry device would increase its R.sub.DSON to such an extent that the figure of merit of the planar structure would be unacceptably high for very low voltage ratings (lower than about 30 volts) application.
Trench devices, however, are difficult to manufacture at very low voltage ratings, because the threshold turn on voltage is low and very thin gate oxides, for example, gate oxides as low as 250 .ANG. thick are needed. These very thin oxides must turn sharp corners in the trench device, leading to serious step coverage problems during manufacture. Consequently, the trench geometry has been very difficult to apply to devices rated at less than about 30 volts.
It would be very desirable to make a low voltage MOSFET, using planar geometry which inherently easily employs thinner gate oxides for reduced threshold turn on voltages, if the figure of merit did not become unduly high when reducing Q.sub.GD, due to an unacceptable increase in R.sub.DSON.